#
# OPTION COMMAND FILE created byCadence Quantus Extraction Version 23.1.1-p051 from CCL
#
capacitance \
	 -decoupling_factor 1.0 \
	 -ground_net "VSS"
device_reduction \
	 -m_factor infinite
extract \
	 -selection "all" \
	 -type "rc_decoupled"
extraction_setup \
	 -array_vias_spacing "auto" \
	 -macro_cells_type "default" \
	 -max_fracture_length infinite \
	 -max_fracture_length_unit "MICRONS" \
	 -max_via_array_size \
		"auto" \
	 -net_name_space "LAYOUT" \
	 -split_via_by_unit_area false
filter_res \
	 -merge_parallel_res false \
	 -min_res 0.001
input_db -type assura \
	 -design_cell_name "Q1.1 layout HW3_evansoan" \
	 -directory_name "/home/evansoan/hw3" \
	 -format "DFII" \
	 -library_definitions_file "/home/evansoan/hw3/cds.lib" \
	 -run_name "HW3"
log_file \
	 -file_name "/home/evansoan/hw3/qrc.HW3.log"
output_db -type extracted_view \
	 -cap_component "pcapacitor" \
	 -cap_property_name "c" \
	 -enable_cellview_check false \
	 -include_cap_model "false" \
	 -include_parasitic_cap_model "true" \
	 -include_parasitic_res_model "comment" \
	 -include_res_model "false" \
	 -res_component "presistor" \
	 -res_property_name "r" \
	 -view_name "av_extracted"
output_setup \
	 -directory_name "/home/evansoan/hw3" \
	 -temporary_directory_name "HW3"
process_technology \
	 -technology_corner \
		"rcx_typical" \
	 -technology_library_file "/opt/eda/cadence/local/gpdk045_v_6_0/assura_tech.lib" \
	 -technology_name "gpdk045_av" \
	 -temperature \
		"25.0"


